The present invention relates to integrated circuits and, more particularly to a design for minimizing crosstalk between parallel signal paths in an integrated circuit. A major objective of the present invention is to provide for higher performance integrated circuits by minimizing crosstalk-induced propagation delays and crosstalk-induced variances in propagation times.
Much of modern progress is associated with advances in computer technology, which in turn has been made possible by continuing advances in integrated-circuit manufacturing technology. In particular, the increasing miniaturization of integrated-circuit features has made possible more functionality (as circuit density has increased) and greater speeds (in part because signal-path distances have diminished).
Integrated circuits typically comprise active elements, such as transistors, and an interconnect structure connecting the active elements to achieve the desired functionality. The interconnect structure includes metal conductors that are electrically isolated from each other, where necessary, by dielectric material such as silicon dioxide. As signals can weaken over long transmission distances, buffers (usually inverters) are often spaced along a signal path. As is well known, two metal layers spaced from each other by dielectric material form a capacitor. Accordingly, neighboring metal conductors separated by dielectric material are capacitively coupled.
The capacitive coupling between conductors can cause crosstalk, the mutual interference of two signals that are supposed to be independent. It can take the form of transitions in one signal (the xe2x80x9caggressorxe2x80x9d) causing artifacts in another signal (the xe2x80x9cvictimxe2x80x9d); the interference can mask, distort, or otherwise disturb the intended form of the signal.
Crosstalk can also cause propagation delays. Computers often transmit information in binary form in which low and high logic levels are represented respectively by low and high voltages. Transitions between low and high voltages inherently take some time (in addition to the signal transit time from driver to receiver). If a parallel aggressor signal undergoes a transition in the opposite direction, the transition time for the victim signal increases. For example, if the aggressor signal transitions from 5 volts to 0 volts while the victim signal transitions from 0 volts to 5 volts, detection of the later transition will be delayed relative to a detection that would have occurred had there been no transition in the aggressor signal. In effect, the maximum propagation time is increased by the crosstalk. The performance of components relying on accurate detection of the victim signal must be limited to accommodate this crosstalk-induced propagation delay. Accordingly, overall circuit performance is impaired by crosstalk-induced propagation delay.
If the aggressor signal transitions in the same direction as the victim signal, the transitions are facilitated and propagation time is decreased. If a transition is detected sooner than expected, it can interfere with the intended reading of a previous signal level. Thus, the rate at which transitions are encoded into a signal must be kept low enough to ensure that the appropriate bit of information is being read. In other words, crosstalk increases the variance (or xe2x80x9ctiming uncertaintyxe2x80x9d) of signal propagationxe2x80x94and overall circuit performance must be limited to ensure accurate readings.
In summary, crosstalk between extended parallel signal paths decreases circuit performance because: 1) the maximum propagation delay is increased; and 2) the variance of the propagation delay is increased. What is needed is a scheme for reducing the performance penalty attributable to such crosstalk.
The present invention provides for inverting the relative sense of parallel signals at least once during transit along their common extent so that the propagation time increases causes by opposing transitions is at least partially compensated by propagation time decreases caused by same-sense transitions.
For example, consider two parallel signals that undergo simultaneous low-to-high voltage transitions at the input to their respective parallel signal paths. Mid-way along the common extent of the paths, one of the signals is inverted while the other is not so that the transitions are now opposing. In this case, both signals will undergo a propagation time increase for the first half of the transmission and a propagation time decrease for the second half of the transmission. Ideally, the increase and decrease would be equal and there would be no variance in propagation times. However, the invention provides an advantage over the prior art even where the increase and decrease are not equal. More generally, the signals should have the same sense for at least one-third of the common path length and the opposite sense for at least a (different) one-third of the common path length.
Two signals have the same relative sense while they have their original senses and while both have a sense opposite their original senses. Two signals have different relative senses when one signal has its original sense and the other has the sense opposite its original sense. Similarly, two transitions have the same sense if they are both low to high or both high to low; two transitions have the opposite sense if one is low to high and the other is high to low.
The inversion can be achieved by inserting a sense-inverting buffer (an inverter) midway along one signal path but not along the other. In this case, the inverter would not only invert the relative sense but also introduce a phase delay. The phase delay would move time-aligned transitions out of time alignment. Their mutual influence would be reduced and thus, the compensation of propagation delay or advance would be reduced. Accordingly, it is preferable that the signal paths have the same number of buffers.
In a first realization of the invention, each sense-inverting buffer on a signal path is adjacent a sense-preserving buffer on an adjacent parallel signal path. The parallel signal paths can be on the same metal level or on different metal levels. Herein, signal paths are adjacent where there is no parallel signal path between them.
One signal path can have a sense-inverting buffer midway along its extent, while the second signal path can have a sense-preserving buffer adjacent to the sense-inverting buffer. Complementarily, the second signal path can also have a sense-inverting buffer adjacent to a sense-preserving buffer of the first signal path. Herein, a point or buffer A is xe2x80x9cadjacentxe2x80x9d to a point or buffer B, if it is nearer to B than to any driver, load, or other buffer on the same signal path as B. xe2x80x9cImmediately adjacentxe2x80x9d in this context means that a projection of A onto the path containing B intersects B.
In a second realization of the invention, parallel signal paths include only sense-inverting buffers, but they are staggered so that the inversions along the respective signal paths take place at different points along the common extent of the paths. While this alternative uses the same number of buffers for each signal path, the parallel signals go in and out of phase in a manner that limits compensation of crosstalk induced propagation variances. Thus, the first realization achieves higher performance at the cost of the inclusion of the sense-preserving buffers.